1. Field of the Invention
This invention relates to a field discrimination circuit used in a display signal processing circuit such as that incorporated in, for example, picture display apparatus (especially, various kinds of flat panel displays, liquid crystal displays and plasma displays) in which individual picture elements or individual scanning lines are fixed on a screen.
2. Description of the Related Art
First, a method for driving a picture display device will be briefly described.
FIG. 1 is a schematic plan view of an example of known picture display devices 50 employed in the present invention. The illustrated picture display device 50 can display 440 scanning lines l.sub.1 to l.sub.440. The odd-numbered scanning lines l.sub.1, l.sub.3, . . . , l.sub.439 are those belonging to a second field, while the even-numbered scanning lines l.sub.2, l.sub.4, . . . , l.sub.440 are those belonging to a first field.
FIG. 2 is a block diagram showing a circuit related to field discrimination in a drive circuit used for driving such a prior art picture display device 50. This drive circuit includes a decoder/vertical driver 51, a vertical address counter 52 and a latch circuit 53 for the field discrimination purpose. The vertical address counter 52 generates count data synchronous with a horizontal synchronizing signal H. The decoder/vertical driver 51 reads out vertical deflection data corresponding to the count data from a memory (not shown) and decodes the vertical deflection data to supply the decoded data to a vertical deflection electrode unit (not shown). The vertical address counter 52, which is reset by a vertical synchronizing signal Vin, counts the pulses of the horizontal synchronizing signal H. The field discrimination latch circuit 53 receives a signal H.sub.F with the timing of the vertical synchronizing signal Vin applied as a clock signal. The field discrimination latch circuit 53 generates a field discrimination output signal FLD which is applied to an LSB (least significant bit) terminal of the decoder/vertical driver 51.
FIG. 3 is a timing chart for illustrating the operation of the drive circuit shown in FIG. 2. In FIG. 3, S.sub.P designates a picture signal of a first field, and S.sub.S designates a picture signal of a second field. The horizontal synchronizing signal H has a pulse internal of one horizontal scanning period, and the signal H.sub.F applied to the field discrimination latch circuit 53 has also a pulse internal of one horizontal scanning period for the purpose of field discrimination. The duty factor of this pulse signal H.sub.F is 50%. The field discrimination output signal FLD of the latch 53 has a waveform as shown in FIG. 3. Va, Vb, Vc and Vd represent four different forms of the vertical synchronizing signal Vin. That is, these signals Va to Vd have different delay times attributable to, for example, variations of the constants of a vertical hold circuit (not shown). Of course, an inverse interlace or an interlace stop should not occur regardless of application of the vertical synchronizing signal Vin having whatever delay time. The numerals appearing beneath the waveforms of the vertical synchronizing signals Va to Vd indicates the counts of the vertical address counter 52.
The operation of the prior art drive circuit driving the known picture display device 50 will now be described with reference to FIGS. 2 and 3. For the purpose of description, it is supposed that the decoder/vertical deriver 51 is designed so that display of a picture is started from the time where the count of the vertical address counter 52 is "20".
First, a description will be directed to the case where the vertical synchronizing signal Vin is represented by Va. In the case of the first field, the vertical synchronizing signal Va is applied with the timing where the signal H.sub.F is in its "L" level. As a result, the field discrimination output signal FLD of the latch 53 is turned into its "L" level. Further, when the screen is scanned with the scanning line l.sub.2, a picture signal portion corresponding to the count "20" of the vertical address counter 52, that is, a picture signal portion .circleincircle.2 is displayed on the screen. Similarly, a picture signal portion .circleincircle..varies.is then displayed when the screen is scanned with the scanning line l.sub.4.
In the case of the second field, the vertical synchronizing signal Va is applied with the timing where the signal H.sub.F is in its "H" level. As a result, the field discrimination output signal FLD of the latch circuit 53 is turned into its "H" level, and a picture signal portion .circleincircle.1 and a picture signal portion .circleincircle.3 are sequentially displayed when the screen is scanned with the scanning lines l.sub.1 and l.sub.3 respectively. Such a display mode is shown in FIG. 4 (a).
Description will then be directed to the case where the vertical synchronizing signal Vb is applied. In the first field, the field discrimination output signal FLD of the latch circuit 53 is turned into its "H" level, and the picture signal portions .circleincircle.2 and .circleincircle.4 are sequentially displayed when the screen is scanned with the scanning lines l.sub.1 and l.sub.3 respectively. On the other hand, in the second field, the field discrimination output signal FLD of the latch circuit 53 is turned into its "L" level, and the picture signal portions .circleincircle.3 and .circleincircle.5 are sequentially displayed when the screen is scanned with the scanning lines l.sub.2 and l.sub.4 respectively. Such a display made is shown in FIG. 4 (b).
Display modes, when the vertical synchronizing signals Vc and Vd are similarly applied, are shown in FIG. 4 (c) and 4 (d) respectively.
Thus, when the field is discriminated in the manner described above, a normal interlaced picture can be displayed regardless of the value of a delay in the vertical synchronizing signal separation circuit.
When, in the field discrimination circuit included in the drive circuit described above, the vertical synchronizing signal Vin is applied to the decoder/vertical driver 51 while the level of the signal H.sub.F is changing, the decoder/vertical driver 51 may not detect such a level change of the signal H.sub.F or may be unable to specify the field, resulting in a variation of its output. As a result, the decoder/vertical driver 51 may be unable to ensure the interlacing operation, or its driving operation may become unstable.